1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method for the same. More specifically, the present invention relates to a semiconductor device in which contact between adjacent wires is prevented for increased flexibility in designing a wiring layout, and to an efficient method for manufacturing the same.
2. Description of the Related Art
Conventionally, electrical connecting between adjacent electrodes in a semiconductor device sometimes involves connection of a plurality of wires to one electrode formed on a semiconductor chip, or a semiconductor element (e.g., see Japanese Patent Application Laid-Open (JP-A) Nos. 04-142073, 06-37250, 11-204720, 2000-114452, 2000-307057, 2002-110898, 2003-243436, and 2003-243442).
In such a case it is possible to achieve miniaturization of a semiconductor chip by connecting a plurality of wires, e.g., two wires, to one electrode terminal on the semiconductor chip to reduce number of electrode terminals, which in turn results in semiconductor device size reductions.
JP-A Nos. 04-142073, 06-37250, 11-204720, 2000-114452, 2000-307057, 2002-110898, 2003-243436, and 2003-243442 disclose a semiconductor device in which a plurality of semiconductor chips is stacked on top of each other and connected to each other with wires.
Such a semiconductor device has a plurality of semiconductor chips therein and thus can offer high performance and multifunctionality. In addition, when the semiconductor device is mounted on a system board or the like, it is possible in the system board to reduce the area occupied by the semiconductor device since the semiconductor chips are stacked on top of each other.
Furthermore, in such a semiconductor device with multiple semiconductor chips, an electrode pad of one semiconductor chip is connected to an electrode pad of another by means of a wire, and one of the electrode pads connected together is further connected to an electrode pad of another semiconductor chip, a bonding pad of a wiring board or a bonding lead of a lead frame using another wire.
Because the use of too long wires can be avoided, the semiconductor device with such a configuration is advantageous over a semiconductor device where electrode pads of individual semiconductor chips are connected to bonding pads of a wiring board or bonding leads of a lead frame using different wires. Too long wires result in difficulty in controlling the formation of stable wire loops and, therefore, adjacent wires may be brought in contact with each other upon wiring, undesirably reducing production yields. Moreover, miniaturization (slimming down) of the semiconductor device cannot be achieved due to increased wire loop height. Furthermore, the wires are susceptible to deformation. For this reason, when the wires are to be encapsulated in resin, flowing resin causes adjacent wires to contact each other, resulting in malfunction of the resulting semiconductor device.
As described above, the foregoing configuration is suitable for reduced semiconductor device size. However, wire bonding used to achieve this configuration causes problems described below. Specifically, JP-A Nos. 04-142073, 06-37250 and 11-204720 fail to disclose a specific wiring layout (i.e., the loop shape and method of forming wires) and it appears that the likelihood that adjacent wires contact upon wire formation is high.
JP-A Nos. 2000-307057 and 2004-221264 disclose a method of bonding two wires—first and second wires—to one electrode pad. To be more specific, a bump is previously arranged on an electrode pad of a semiconductor chip, where the two wires are to be bonded. First bonding is performed on an electrode pad of another semiconductor chip, a bonding pad of a wiring board or a bonding lead of a lead frame, followed by second bonding on the bump to form the first wire. Subsequently, first bonding is performed on an electrode pad of another semiconductor chip, a bonding pad of the wiring board or a bonding lead of the lead frame, followed by second bonding on the bump to form the second wire.
General wire bonding operations for the first bonding adopt so-called ball bonding (also referred to as “nail head bonding”) in which a ball is formed by sparking one end of a wire and the resulting ball is bonded to an electrode pad or the like by application of load and ultrasonic vibration through a bonding capillary. The second bonding is performed by means of so-called stitch bonding in which a wire is pressed against an electrode pad or the like at the tip (face) of a bonding capillary. This strategy, however, has a problem that in a case where the second bonding end of the second wire is to be formed on or next to the second bonding end of the first wire on the bump, the bonding capillary undesirably touches the second bonding end of the first wire, which has been formed previously, upon second bonding of the second wire to thereby cause connection deterioration of the second bonding end of the first wire.
JP-A Nos. 2000-114452, 2000-307057, 2002-110898, 2003-243436 and 2003-243442 also disclose a method of bonding two wires on one electrode pad.
To be more specific, a bump is previously arranged on an electrode pad of a semiconductor chip, where two wires are to be bonded. First bonding is then performed on an electrode pad of another semiconductor chip, a bonding pad of a wiring board or a bonding lead of a lead frame, followed by second bonding on the bump to form a first wire. Subsequently, first bonding is performed on an electrode pad of another semiconductor chip, a bonding pad of the wiring board or a bonding lead of the lead frame, followed by second bonding on the bump to form a second wire. Note that so-called ball bonding is generally adopted for the first bonding, and so-called stitch bonding is adopted for the second bonding, as described above.
The shape of a wire loop formed as a result of this general bonding operation is such that it rises upwardly from the first bonding end at the first bonding side, lies horizontally at the second bonding side and gradually rises toward the first bonding end. Thus, wire loop height is high at the first bonding side, whereas it is low at the second bonding side. Thus, similar loop-shaped wires result continuously in a staircase pattern.
When wires are to be encapsulated in sealing resin, it is necessary to arrange the wires so that two adjacent ones intersect, depending on the arrangements of electrode pads on semiconductor chips, bonding pads on the wiring board, and bonding leads on the lead frame. This sometimes makes wire-bonding operations difficult. In addition, if adjacent wires intersect, there will be a problem that the resulting semiconductor device may not operate normally due to contacting wires. For example, as shown in FIG. 1A of JP-A No. 04-142073, short-circuits may occur at wire intersections when similar loop wires are formed continuously in a staircase manner.
A technology has not yet been provided that prevents, upon electrical connection between adjacent electrodes in a semiconductor device by wire bonding, wires from contacting each other for greater flexibility in designing a wiring layout; therefore, a further development is expected to be made.
It is an object of the present invention to solve the foregoing conventional problems and to achieve the object described below.
Specifically, it is an object of the present invention to provide a small, high-performance semiconductor device in which contact between adjacent wires is prevented for increased flexibility in designing a wiring layout, and an efficient method for manufacturing the semiconductor device.